LPSR: Novel Low Power State Retention Technique for CMOS VLSI Design
نویسندگان
چکیده
منابع مشابه
Low Power State Retention Technique for CMOS VLSI Design
Mobile computing and mobile communication applications which are powered by battery, the battery life is a major concern. Leakage power dissipation is critical in VLSI circuits as the battery leaks even when devices are in idle state. To reduce leakage power as well as total power in CMOS logic gates and circuits a new circuit technique called LPSR Technique is proposed in this paper. Earlier w...
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ژورنال
عنوان ژورنال: International Journal of Computer Applications
سال: 2012
ISSN: 0975-8887
DOI: 10.5120/8145-1931